1. Field of the Invention
The present invention relates to a method operable in a parallel test apparatus of memory cells of a memory, in which the memory is divided into groups of memory cells and one group of memory cells is activated by addressing words and/or bit lines of a memory, in which a test pattern is respectively written into all memory cells of the group and respectively all memory cells of the group are subsequently read and the read-out information are supplied to a parallel test mechanism. A first result is calculated, a further test pattern is formed from the test pattern and the further test pattern is written into all memory cells of the same group and is, in turn, subsequently read from all memory cells of the same group and the read-out, further information are supplied to the parallel test mechanism. A second result is calculated.
2. Description of the Prior Art
In the manufacture of semiconductor memories, the time that it takes to test the entire semiconductor memory is to be tested for its operability represents a significant cost factor. The test time also increases to a considerable degree, particularly with increasing size of the memory modules.
Up to now, sequential test methods have been almost exclusively used for checking the operability of memory modules, with the disadvantage of a particularly long testing time. There are therefore efforts to parallelize the sequentially-executed test insofar as possible. A method and an apparatus to parallel test a memory with which it is possible to test four bits of a semiconductor memory in parallel is known from the publication JEDEC Solid State Products Engineering Council, March 1987. Two test patterns that are read parallel into the memory cells are available for such a four-bit parallel method. A first test pattern for this purpose is formed of a sequence of ones and a second test pattern is formed from a sequence of zeros. There is no flexibility in the selection of possible test patterns in this method. Upon reading the result from the memory cells, moreover, only one decision is possible, namely whether there are defective memory cells or whether all memory cells are functional.